A Taxonomy of Parallel Prefix Networks
نویسندگان
چکیده
Parallel prefix networks are widely used in highperformance adders. Networks in the literature represent tradeoffs between number of logic levels, fanout, and wiring tracks. This paper presents a three-dimensional taxonomy that not only describes the tradeoffs in existing parallel pre fix networks but also points to a family of new networks. Adders using these networks are compared using the method of logical effort. The new architecture is competitive in latency and area for some technologies.
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